1. Field of the Invention
The present invention generally relates to a digital phase locked circuit that can not only output a phase locked signal for an input clock signal even if the input clock signal is supplied in a burst fashion but also achieve a satisfactory phase absorption characteristic.
2. Description of the Related Art
In SDH (Synchronous Digital Hierarchy), STM (Synchronous Transport Module)-1 (155 Mbps) is provided as a fundamental frame. In addition, for instance, STM-0, STM-4 and STM-16 are provided as frames for the bit rates 51 Mbps, 622 Mbps and 2.4 Gbps, respectively.
In the SDH and the similar method, SONET (Synchronous Optical Network), a frame comprises an overhead and a payload. For instance, a container C-N (N: 2, 3, 4, 11 and 12) becomes a virtual container VC-N by attaching a path overhead thereto, and then the virtual container VC-N is mapped to a payload for the data transmission. Here, the containers C-11, C-12 and C-2 have bit rates 1.544 Mbps, 2.048 Mbps and 6.312 Mbps, respectively.
In order to demap the transmitted container C-N from the payload, it is necessary to identify the head position of the mapped container C-N based on a pointer thereof and extract the byte-interleaved container C-N. Then, the extracted container C-N, for instance, is written in a memory and is subsequently read from the memory based on a read clock signal whose phase is synchronous with that of the write clock signal that has been generated when the container C-N is written in the memory.
FIG. 1 is a diagram for explaining a conventional demapping process for C-N data. As is shown in FIG. 1, a digital phase locked circuit, which is referred to as a DPLL circuit hereinafter, conventionally comprises a C-N demapping part 51, a memory 52, a phase comparing part 53 and a DPLL (Digital Phase Locked Loop) part 54. The C-N demapping part 51 receives an SDH frame synchronous with a system clock signal. Then, the C-N demapping part 51 demaps target C-N data from the payload of the input SDH frame with reference to the pointer thereof in accordance with the system clock signal. Then, the demapped C-N data are delivered to the memory 52 and are written therein in accordance with a write clock signal WCLK synchronous with the demapped C-N data.
The DPLL part 54 receives a master clock signal and then supplies a read clock signal RCLK. The phase comparing part 53 compares the read clock signal RCLK with the write clock signal WCLK and delivers a phase comparison signal to the DPLL part 54 in order to synchronize the read clock signal RCLK with the write clock signal WCLK. The C-N data are consecutively read from the memory 52 in accordance with the read clock signal RCLK and then are delivered to the next circuit together with the read clock signal as a clock signal of the next circuit.
Based on the phase comparison signal from the phase comparing part 53, which indicates whether the phase of the read clock signal RCLK goes ahead or behind that of the write clock signal WCLK, the DPLL part 54 deletes/inserts one pulse from/into the master pulse or changes a dividing ratio for the master clock signal in order to lock the phase of the read clock signal RCLK with that of the write clock signal WCLK.
In this case, since the C-N data from the C-N demapping part 51 are extracted from the payload of the SDH frame by unit of one byte, the write clock signal WCLK is also synchronized with the C-N data. The phase comparing part 53 compares the phase of the continuous read clock signal RCLK with that of the write clock signal WCLK generated in a burst fashion. Here, the comparing part 53 can be implemented, for instance, with an exclusive OR circuit. When the phase comparing part 53 supplies a phase comparison signal to the DPLL part 54, the DPLL part 54 synchronizes the phase of the read clock signal RCLK with that of the write clock signal WCLK by changing the current dividing ratio for the master clock signal into a more appropriate value or by deleting/inserting one pulse from/into the master clock signal.
In the case where the phase comparison signal is set as an output signal of the exclusive OR of the write clock signal WCLK and the read clock signal RCLK as mentioned above, an up-down counter is provided in the DPLL part 54. The up-down counter counts up/down a counter value thereof while the phase comparison signal is HIGH/LOW, respectively. When the counter value reaches a predetermined value, one pulse is deleted/inserted from/into the master clock signal so as to lock the phase of the read clock signal RCLK with the write clock signal WCLK. Namely, such an up-down counter serves as a low path filter of the phase locked loop.
Japanese Laid-Open Patent Application No. 06-053821 discloses a DPLL circuit for producing an output clock signal whose phase is synchronous with that of an input clock signal. In this DPLL circuit, an up-down counter is used to compare the phase of the output clock signal with the phase of the input clock signal like the above-mentioned conventional DPLL circuit. Based on a comparison result, a pulse is deleted/inserted so that the output clock signal can be locked with the input clock signal. Here, the DPLL circuit measures a phase difference between the output clock signal and the input clock signal and then classifies the phase difference into two or three classes, that is, a large difference class and a small difference class or a large difference class, a medium difference class and a small difference class. If the measured phase difference is classified into the small difference class, one pulse of the system clock signal is deleted/inserted from/into the output clock signal for the phase control of the output clock signal. If the measured phase difference is classified into the large difference class, a pulse of a clock signal generated by dividing the system clock signal is deleted/inserted. Namely, it is possible to flexibly control the phase of the output clock signal by deleting/inserting a plurality of pulses of the system clock signal. As a result, it is possible to not only achieve speedy phase synchronization but also suppress jitter after the phase synchronization.
Japanese Laid-Open Patent Application No. 07-086926 discloses another DPLL circuit related to the present invention. In a PON (Passive Optical Network), even if sender timings for sending signals from a plurality of child stations to a parent station are set in advance, intervals between receiver timings when the parent station receives the signals from the child stations are not deterministic. This situation is substantially equivalent to a case where the parent receives signals from child stations in a burst fashion. In this case, the parent station uses the DPLL circuit to generate a higher-speed clock signal for identifying the received signals from the child stations. A plurality of shift registers delay the received signals in accordance with the higher-speed clock signal so that the received signals can have different delay times from each other. Then, individual phases of the delayed received signals are compared with that of the clock signal of the parent station. The DPLL circuit identifies the data from the child station having the received signal whose phase is equal to the phase of the parent station.
In the DPLL circuit according to Japanese Laid-Open Patent Application No. 06-053821, the DPLL circuit produces an output clock signal synchronous with an input clock signal. The DPLL circuit uses an up-down counter thereof to count the counter value based on a phase comparison result indicating whether the phase of the input clock signal goes ahead or behind the phase of the output clock signal. If the counter value reaches a predetermined value, one pulse of a master clock signal is deleted/inserted from/to the output clock signal. The DPLL circuit determines a phase difference between the input clock signal and the output clock signal and controls the quantity of insertions and deletions of the master clock corresponding to the phase difference. As a result, it is possible to not only achieve the phase synchronization at high-speed but also suppress jitter.
However, when the DPLL circuit is used to process C-N data demapped from a payload of an SDH frame, there arise some problems. In this case, the C-N data tend to be supplied in a burst fashion. Also, regarding position of the C-N data in SDH frames, the C-N data may be located at the same position for all the SDH frames or may be located at different positions for the individual SDH frames. Therefore, there is a probability that the demapped C-N data are not input in a constant time interval. In order to address such a situation, the DPLL circuit for processing C-N data is required to output a clock signal synchronous with the phase of the C-N data.
In the DPLL circuit according to Japanese Laid-Open Patent Application No. 07-086926, when the demapped C-N data are supplied in a burst fashion, the DPLL circuit may be designed to shift the demapped C-N data by using a plurality of shift registers so as to obtain a clock signal synchronous with the output data from the shift registers. However, since the plurality of the shift registers are provided in the DPLL circuit, the DPLL circuit becomes large in size. In addition, the DPLL circuit has difficulty in following phase variations of the input data.
Furthermore, a DPLL circuit is required to satisfy a predetermined MTIE (Maximum Time Interval Error) standard. As mentioned in Japanese Laid-Open Patent Application No. 06-053821, the DPLL cannot satisfy the predetermined MTIE standard by simply inserting/deleting a low-frequency pulse such as the master clock signal or a high-frequency pulse such as the output divided signal into/from the output clock signal in accordance with the phase difference. In other words, the DPLL circuit cannot achieve the satisfactory phase synchronization characteristic.